-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"

-- DATE "12/02/2023 16:38:57"

-- 
-- Device: Altera EP4CE6E22C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	dig_select_021 IS
    PORT (
	dig_021 : OUT std_logic_vector(5 DOWNTO 0);
	add_021 : IN std_logic_vector(2 DOWNTO 0)
	);
END dig_select_021;

-- Design Ports Information
-- dig_021[5]	=>  Location: PIN_1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- dig_021[4]	=>  Location: PIN_2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- dig_021[3]	=>  Location: PIN_7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- dig_021[2]	=>  Location: PIN_10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- dig_021[1]	=>  Location: PIN_11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- dig_021[0]	=>  Location: PIN_30,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- add_021[0]	=>  Location: PIN_24,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- add_021[2]	=>  Location: PIN_25,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- add_021[1]	=>  Location: PIN_28,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF dig_select_021 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_dig_021 : std_logic_vector(5 DOWNTO 0);
SIGNAL ww_add_021 : std_logic_vector(2 DOWNTO 0);
SIGNAL \dig_021[5]~output_o\ : std_logic;
SIGNAL \dig_021[4]~output_o\ : std_logic;
SIGNAL \dig_021[3]~output_o\ : std_logic;
SIGNAL \dig_021[2]~output_o\ : std_logic;
SIGNAL \dig_021[1]~output_o\ : std_logic;
SIGNAL \dig_021[0]~output_o\ : std_logic;
SIGNAL \add_021[1]~input_o\ : std_logic;
SIGNAL \add_021[0]~input_o\ : std_logic;
SIGNAL \add_021[2]~input_o\ : std_logic;
SIGNAL \inst|15~0_combout\ : std_logic;
SIGNAL \inst|15~1_combout\ : std_logic;
SIGNAL \inst|15~2_combout\ : std_logic;
SIGNAL \inst|15~3_combout\ : std_logic;
SIGNAL \inst|15~4_combout\ : std_logic;
SIGNAL \inst|15~5_combout\ : std_logic;
SIGNAL \inst|ALT_INV_15~5_combout\ : std_logic;
SIGNAL \inst|ALT_INV_15~4_combout\ : std_logic;
SIGNAL \inst|ALT_INV_15~3_combout\ : std_logic;
SIGNAL \inst|ALT_INV_15~2_combout\ : std_logic;
SIGNAL \inst|ALT_INV_15~1_combout\ : std_logic;
SIGNAL \inst|ALT_INV_15~0_combout\ : std_logic;

BEGIN

dig_021 <= ww_dig_021;
ww_add_021 <= add_021;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\inst|ALT_INV_15~5_combout\ <= NOT \inst|15~5_combout\;
\inst|ALT_INV_15~4_combout\ <= NOT \inst|15~4_combout\;
\inst|ALT_INV_15~3_combout\ <= NOT \inst|15~3_combout\;
\inst|ALT_INV_15~2_combout\ <= NOT \inst|15~2_combout\;
\inst|ALT_INV_15~1_combout\ <= NOT \inst|15~1_combout\;
\inst|ALT_INV_15~0_combout\ <= NOT \inst|15~0_combout\;

-- Location: IOOBUF_X0_Y23_N2
\dig_021[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|ALT_INV_15~0_combout\,
	devoe => ww_devoe,
	o => \dig_021[5]~output_o\);

-- Location: IOOBUF_X0_Y23_N9
\dig_021[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|ALT_INV_15~1_combout\,
	devoe => ww_devoe,
	o => \dig_021[4]~output_o\);

-- Location: IOOBUF_X0_Y21_N9
\dig_021[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|ALT_INV_15~2_combout\,
	devoe => ww_devoe,
	o => \dig_021[3]~output_o\);

-- Location: IOOBUF_X0_Y18_N16
\dig_021[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|ALT_INV_15~3_combout\,
	devoe => ww_devoe,
	o => \dig_021[2]~output_o\);

-- Location: IOOBUF_X0_Y18_N23
\dig_021[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|ALT_INV_15~4_combout\,
	devoe => ww_devoe,
	o => \dig_021[1]~output_o\);

-- Location: IOOBUF_X0_Y8_N16
\dig_021[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|ALT_INV_15~5_combout\,
	devoe => ww_devoe,
	o => \dig_021[0]~output_o\);

-- Location: IOIBUF_X0_Y9_N8
\add_021[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_add_021(1),
	o => \add_021[1]~input_o\);

-- Location: IOIBUF_X0_Y11_N15
\add_021[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_add_021(0),
	o => \add_021[0]~input_o\);

-- Location: IOIBUF_X0_Y11_N22
\add_021[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_add_021(2),
	o => \add_021[2]~input_o\);

-- Location: LCCOMB_X1_Y20_N0
\inst|15~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|15~0_combout\ = (!\add_021[1]~input_o\ & (\add_021[0]~input_o\ & \add_021[2]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100010000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \add_021[1]~input_o\,
	datab => \add_021[0]~input_o\,
	datad => \add_021[2]~input_o\,
	combout => \inst|15~0_combout\);

-- Location: LCCOMB_X1_Y20_N10
\inst|15~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|15~1_combout\ = (!\add_021[1]~input_o\ & (!\add_021[0]~input_o\ & \add_021[2]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001000100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \add_021[1]~input_o\,
	datab => \add_021[0]~input_o\,
	datad => \add_021[2]~input_o\,
	combout => \inst|15~1_combout\);

-- Location: LCCOMB_X1_Y20_N12
\inst|15~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|15~2_combout\ = (\add_021[1]~input_o\ & (\add_021[0]~input_o\ & !\add_021[2]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \add_021[1]~input_o\,
	datab => \add_021[0]~input_o\,
	datad => \add_021[2]~input_o\,
	combout => \inst|15~2_combout\);

-- Location: LCCOMB_X1_Y20_N30
\inst|15~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|15~3_combout\ = (\add_021[1]~input_o\ & (!\add_021[0]~input_o\ & !\add_021[2]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \add_021[1]~input_o\,
	datab => \add_021[0]~input_o\,
	datad => \add_021[2]~input_o\,
	combout => \inst|15~3_combout\);

-- Location: LCCOMB_X1_Y20_N24
\inst|15~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|15~4_combout\ = (!\add_021[1]~input_o\ & (\add_021[0]~input_o\ & !\add_021[2]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \add_021[1]~input_o\,
	datab => \add_021[0]~input_o\,
	datad => \add_021[2]~input_o\,
	combout => \inst|15~4_combout\);

-- Location: LCCOMB_X1_Y20_N2
\inst|15~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|15~5_combout\ = (!\add_021[1]~input_o\ & (!\add_021[0]~input_o\ & !\add_021[2]~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000010001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \add_021[1]~input_o\,
	datab => \add_021[0]~input_o\,
	datad => \add_021[2]~input_o\,
	combout => \inst|15~5_combout\);

ww_dig_021(5) <= \dig_021[5]~output_o\;

ww_dig_021(4) <= \dig_021[4]~output_o\;

ww_dig_021(3) <= \dig_021[3]~output_o\;

ww_dig_021(2) <= \dig_021[2]~output_o\;

ww_dig_021(1) <= \dig_021[1]~output_o\;

ww_dig_021(0) <= \dig_021[0]~output_o\;
END structure;


